RTL Design & Implementation of a RISC Processor and Peripheral Multiplexer -Part II
Here is the second part of the RISC Processor Design. I have implemented this Processor as a part of my ASIC Design Lab project “Programmable Controller/Router and Peripheral Design with peripheral I/O multiplexing”. This project focuses of peripheral multiplexing to the GPIO pins of the processor in runtime. An example case will be a […]