RTL Design & Implementation of a RISC- Single Cycle Processor -Part I

  Low cost FPGA development platforms and Hardware Description Languages like Verilog & VHDL have not only made lives of Front-end VLSI  Engineers easier but also hobbyists’ . I have been experimenting with a 40$ Xilinx FPGA development board for couple of years and its real fun. And now, a part of my project for ASIC Design Lab course at University of Minnesota requires me to design and implement a microprocessor. Armed with my FPGA board and a new-found enthusiasm amidst my busy schedule at the U of M, I sat up to design a minimalistic CPU in Verilog.

1. Verilog/VHDL Simulator (ModelSim, Icarus Verilog, Xilinx ISE,etc)
2. A decent Code Editor (VIM)
3. A Xilinx FPGA board (optional)

  I chose Load/Store Architecture for my microprocessor design since most RISC machines like ARM, MIPS,etc are based on this architecture. Besides that, quicker prototyping and better understanding of computer architecture was on top priority in my list in this project. And the design is loosely based on MIPS architecture since I designed a custom 16-bit Instruction Set Architecture similar to MIPS ISA.

1. 16-bit Reduced Instruction Set
2. Integrated with peripherals like UART, TIMER, GPIO and Peripheral Multiplexer
3. Planned Support of run-time programming (Doesn’t require reprogramming the entire processor core)

1. Program Counter
2. Instruction Memory
3. Register File
4. ALU

BLOCK DIAGRAM:

Program Counter:

  Program counter(PC) counts and generates the address of the memory where the next instruction is waiting to be executed. Here let us assume that the memory address range is 0-127. So we need a 7-bit counter to generate instruction addresses. A Logisim simulation of a positive edge triggered simple counter is shown below.

Instruction Memory and Register:

  Here for simplicity, instruction memory can store 128 16-bit wide instructions. And I have provided a write functionality to write into the instruction memory so that it can be programmed in run-time while running in the FPGA. And register file has 16 registers of 8-bit width each. When the address is generated and fed to the instruction memory by the program counter, the particular instruction is fetched. The register type instruction is has a opcode, two source registers and one destination register. Opcode determines the type of operation to be performed on the operands. for example, 0000 stands for add instruction.

  For now, the ALU supports minimal instructions like ADD, SUB, AND, OR and NOT functions. More instructions like branch instructions, LOAD &  STORE will be discussed in part II. 

  The project is created in Xilinx ISE and simulated using ISIM simulator. Here a testbench is written to simulate an ADD instruction. The instruction is fetched, decoded and executed in single clock cycle. The waveforms are plotted below.

Rest of the modules, data path and support for branch instructions will be covered in Part II.