by Having worked with a variety of microcontrollers from AVR to ARM Cortex controllers, I bought a Xilinx FPGA dev board(papilio One) which around $40 to experiment. After getting comfortable with Verilog HDL, I implemented few data encoders-decoders, communication blocks and played around a while.
Then my attention turned towards implementing a Soft-core Processor in FPGA. But I need my own instruction set and a Compiler for my soft-processor too. Besides, intensive googling taught me that there are tons of Soft-processor cores.
Finally,I settled with ZPU which a 32-bit softcore processor for xilinx FPGA with good amount of peripherals ranging from timers to communication blocks like UART, SPI etc. It has support for VGA screen drivers too.
PROJECT:
This project was aimed to implement a system to play a small snippet of audio from FPGA’s memory using ZPU – soft-core processor.
Components used:
- Papilio One board- Xilinx Spartan XC3S250E
- A speaker
- Misc- Resistors and capacitors
BLOCK DIAGRAM:
The audio signal is recorded in nero wave editor and converted to 8-bit, 8000samples/second mono PCM wave format. This audio data from this file is extracted using FILE I/O functions in Cpp and stored as and array. This array of data is written to a file in the format of a variable array holding these values. This variable array is used in soft processor code.
The audio data looks as follows:
The PWM feature is used to generate analog audio output from the given data. I have used 80khz as carrier wave which is 10 times that of sampling rate(8000).
PWM frequency= 10 x sampling rate = 10 x 8000 = 80KHz
This means that we have 10 PWM waves per sample to represent the analog voltage. The duty cycle of these waves are varied to generate the required voltage level.
Duty cycle = % of time for which the wave is logic “HIGH” ie. Ton /(Ton+Toff)
Since the audio data is 8 bit wide, the values range from 0-255 ( 0 – 2^8); which means 0 corresponds to 0% duty cycle and 255 corresponds to 100% duty cycle.For example, if sample 1 has the value 127, 10 waves with 50% duty cycle are generated immediately to generate the voltage (Around 1.65V = 50% of 3.3V)
So repeating the above process for all the 8000 samples per second, we can generate a decent analog wave form similar to the audio data.
DEMO:
Here I have recorded my name “Bharathi” and stored as array of data in the code and programmed the FPGA. The audio quality is bearable since I have used a tiny piezo speaker and I have not used proper filtering of noise using RC filter(LPF mostly).
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